The POWER of FPGAs

Written by Ian on Wednesday 22/08/07

Proponents know they can do a lot. But how much processing can we do with an FPGA and how does this compare with a DSP or fast CPU? This article attempts to find out...

Simple ROM VHDL code example.

Written by Tom on Monday 04/06/07

ROM is used to store predetermined values. This might be some boot code for a VHDL micro implementation, or maybe a set of tap weights for a FIR filter

Simple fixed point divider VHDL code example.

Written by Tom on Monday 04/06/07

Here is a fixed point divider with remainder written in combinational logic

VHDL Data-path Optimisation; Race Conditions, Pipelining and Critical path overview.

Written by Tom on Wednesday 30/05/07

There are a couple of data-path conditions in VHDL design that will cause the code to fail, race condition and the opposite propagation delay

How to cross Clock domains safely VHDL tutorial.

Written by Tom on Tuesday 29/05/07

In this article we will explain the dangers of crossing clock domains and propose methods to do it safely.

Crossing clock domains without precautions can cause problems due to timing issues;

• Setup and Hold violations

• Metastability conditions

• Unreliable data

Simple Debounce VHDL example code.

Written by Tom on Monday 28/05/07

Any FPGA that has external signals via a pushbutton will suffer from contact bounce.

Definition:

Contact bounce (also called chatter) is a common problem with mechanical switches and relays

An overview of Clock Skew in Synchronous VHDL designs.

Written by Tom on Monday 28/05/07

The golden rule in VHDL design is ‘All code will be synchronous.’ Synchronous circuits are susceptible to a couple of problems one of which is clock skew.

Clock skew (sometimes called timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as

Designing Reliable VHDL Finite State Machines.

Written by Tom on Friday 25/05/07

In this article we discuss how to design a reliable Finite State Machine by following the below VHDL design rules.

1. Use a two process Entity structure.

2. Selection of encoding style.

3. Ensure all signals used in the Process appear in the process list.

4. Ensure all combinations of input/output signals are included in the code.

5. Ensure all outputs of the FSM are registered.

6. Ensure all input are synchronous

Simple SPI Master Slave VHDL example code.

Written by Tom on Sunday 20/05/07

SPI is a simple interface with high data rates, we have had SPI running at 1 MHz over short distances. The only precaution we had to take was to run a ground with every signal wire

Simple SPI Master VHDL example code.

Written by Tom on Thursday 10/05/07

SPI is a simple interface with high data rates we have had SPI running at 1 MHz over short distances

Simple FIR VHDL example code.

Written by Tom on Monday 09/04/07

This is a simple 4 tap FIR. This is a dedicated filter. A general purpose filter will be worked on later

Simple MAC (multiply-accumulate) VHDL example code.

Written by Tom on Friday 30/03/07

The role of a MAC is to add two numbers together and then add the result to the previously accumulated value, which is then restored in the registers for future accumulation

Nasty GHDL/GTKWave bug, (signal reg).

Written by Tom on Thursday 29/03/07

Came across a nasty bug either in GHDL or GTKWave.

In the below code, if reg is defined then GTKWave will give me the following error

Simple FIFO, VHDL example code.

Written by Tom on Monday 19/03/07

This is a working example of a simple FIFO complete with
full and empty signals, over flow and under flow protection

Simple ALU VHDL example code.

Written by Tom on Friday 16/03/07

This a working example of a simple Arithmetic Logic Unit implemented in VHDL.

You can get a simple ALU from

Simple RAM block with Bidirectional data bus, VHDL example code.

Written by Tom on Thursday 15/03/07

This is just a variation to the previously posted Simple RAM block example.

You can get a simple VHDL RAM block with

Simple RAM block, VHDL example code

Written by Tom on Thursday 22/02/07

FPGA’s are useful in various number crunching applications. Being able to complete 32/64 bit multiplications every clock cycle you can process a lot of data quickly. The place to store the pre-processed and processed data is the RAM block

VHDL Simple Serial Tx/Rx, VHDL example code.

Written by Ian and Tom on Wednesday 21/02/07

This is a complete VHDL serial solution with test bench and GTKWave signals. You can get it from

VHDL simple serial receiver code example.

Written by Tom on Wednesday 14/02/07

One of the easiest ways to communicate with an FPGA is via a standard RS232 serial port.
The IO pins from the FPGA are not likely to be RS232 compatible so you must use a voltage shifter

Installing GHDL and Compiling VHDL with GHDL tutorial.

Written by Tom on Tuesday 13/02/07

I’m stuck in the hills of Pakistan and don’t have US$1000 to buy a license for Altera Quartus II tool chain. So what can I use to compile and debug some VHDL code? GHDL is a

Xemacs and VHDL tutorial.

Written by Tom on Friday 02/02/07

Xemacs is a highly configurable editor. It has a VHDL extension which is very powerful. In this article I will briefly outline the basics of Xemacs;

Installation.

Adding the vhdl package.

Some nice features of the VHDL extension

Biggest FPGA manufactueres

Written by Ian on Sunday 14/01/07

Altera and Xilinx fight it out in the marketplace

How to Teach Yourself VHDL.

Written by Tom on Tuesday 12/12/06

A few years back I had an opportunity to work with FPGA's but first I had to teach myself VHDL