Nasty GHDL/GTKWave bug, (signal reg).

Written by Tom on Thursday 29/03/07


Came across a nasty bug either in GHDL or GTKWave.


In the below code, if reg is defined then GTKWave will give me the following error
Solution from developer:

Follow-up Comment #1:

Hi,

reg is a Verilog keyword. It can't be used as a signal name in
a vcd file.


Although ghdl might avoid this issue, either rename the signal
or use --wave option (instead of --vcd).


Tristan.

----


Came across a nasty bug either in GHDL or GTKWave.


In the below code, if reg is defined then GTKWave will give me the following error


$VAR parse error encounter.


1 VCD parse errors encounter, exiting.


===== code ====

architecture a of bug_tb is

-- signal reg : signed(7 downto 0);

signal reg1 : signed(7 downto 0);

-- clock

signal clk : std_logic := '1'

-- reset

signal rst : std_logic := '1'

begin -- a

clk <= not clk after 5 ns; -- 10 ns period

rst <= '0' after 5 ns;

-- waveform generation

WaveGen_Proc: process

begin

-- insert signal assignments here

wait until Clk = '1'

wait until Clk = '1'

assert false report "end of test" severity note;

wait;

end process WaveGen_Proc;

end a;

=============


If I change reg to reg1 no worries.


No idea what the problem is but it did take me a couple of hours to figure it out.


Download the project from here.


Use the go.bat to compile and run GTKWave.