Simple SPI Master Slave VHDL example code.

Written by Tom on Sunday 20/05/07


SPI is a simple interface with high data rates, we have had SPI running at 1 MHz over short distances. The only precaution we had to take was to run a ground with every signal wire.


Here is a simple VHDL SPI implementation. It has a fixed data word of 16 bits.
Set the StartTx high for a min of one clk cycle to kick off the Master.


Note: The data rate is a quarter the clk signal speed.


The Master implementation is a simple Finite State Machine (FSM) and the Slave implementation is combinational logic.


From GTKWaveSignals.JPG the results of the simulation can be seen.


Download the project from here.