An overview of Clock Skew in Synchronous VHDL designs.

Written by Tom on Monday 28/05/07

The golden rule in VHDL design is ‘All code will be synchronous.’ Synchronous circuits are susceptible to a couple of problems one of which is clock skew.

Clock skew (sometimes called timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as;

• wire-interconnect length,

• temperature variations,

• variation in intermediate devices,

• capacitive coupling,

• material imperfections,

• and differences in input capacitance on the clock inputs of devices using the clock.

As the clock rate of a circuit increases timing becomes more critical and there is less variation that can be tolerated while still functioning properly

In an ideal VHDL synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level change of the system clock. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behavior of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed at which each synchronous system can run.

There are two types of clock skew positive skew and negative skew.

Positive skew is when the clock reaches the receiving register later than it reaches the register sending data to the receiving register.

Negative skew is the opposite, when the receiving register gets the clock earlier than the sending register.

There are two types of violations that can be caused by clock skew.

The first violation is caused when the clock travels slower than the path from one register to another - allowing data to penetrate two registers in the same clock tick, or might destroy the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through.

The second violation is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew can cause both violations, but negative skew can never cause a hold violation.

Phase-locked loops.

Phase-locked loops are used by FPGA manufactures to control, and generate clock signals.
Typically there is one input system clock generated from an external clock chip and fed into the FPGA via a dedicated global clk pin. From here the PLL can be used to create others clocks that are multiples of the system clock. Each new clock requires FPGA resources. The greater the division or multiplication required to generate the new clock signal the greater the use of resources. It is not uncommon to define a clock signal via the PLL component and be told that there are no resources available to implement it.

Delay-locked loop.

Delay-locked loop is used to recover clock signal on high speed data transfers. i.e. LVDS.
If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a de-skew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a Delay-Locked Loop (DLL) is frequently used.

Techniques used to limit clock skew.

FPGA makers go to great lengths to ensure that clock skew is kept to a minimum. Their clock skew specifications are part of the propaganda war between manufactures. Here is how Altera minimizes clock skew.

• Programmable Phase Shift

• Programmable Delay Shift

• Clock Switchover

• PLL Reconfiguration

• Programmable Bandwidth

• Spread-Spectrum Clocking

Clock Network design.

Each Stratix device has up to 16 high-performance,
low-skew global clocks that can be used for clocking high-performance functions or global control lines. Additionally, six localized (regional) clocks per region increase the total number of clocks for any region to 22. This web of high-speed clock lines, which are tightly coupled with the abundant PLLs, ensures that the most complex design can run at optimal performance and with minimum clocking skew.

System-Level Clock Management.

Each Stratix device has two PLLs with dedicated outputs to manage board level system timing. There are up to a total of 16 single-ended or eight differential outputs. These outputs can be used to provide clocks to other devices in the system, eliminating the need for other clock sources on the board. Users can utilize a combination of the features provided in the Stratix PLLs, such as programmable phase shift, external feedback, and delay to compensate for board-level skew and delays.


Clock skew is problematic in synchronous FPGA circuits. It will cause devices to fail due to setup and hold violations. The clock skew also sets the upper frequency at which the device can function at. Most manufactures provide methods to minimize this effect. The routing of multiple clock lines provides a matrix of high speed clock lines that reduces clock delay. Enhanced Phase-locked loops are used for clock generation and control further reducing clock skew and finally Delayed-locked loop are used for clock recovery on high speed data links.

I do not claim any originality in this article.