How to cross Clock domains safely VHDL tutorial.

Written by Tom on Tuesday 29/05/07


In this article we will explain the dangers of crossing clock domains and propose methods to do it safely.


Crossing clock domains without precautions can cause problems due to timing issues;


• Setup and Hold violations

• Metastability conditions

• Unreliable data


Below are some methods to ensure correct data transfer across clock domains.


simpleStrobeRequest


Simple Parallel Strobe.

A simple parallel data interface (and some serial interfaces) use DATA and STROBE (i.e. "data clock") signals provided by the sender(Master). The receiver (Slave) must be fast enough to read the data.


Simple Parallel Request.

Alternatively, the receiver (Master) may REQUEST the data. The sender (Slave) must provide data at requested rate.


twoCycleHandShake


Two-cycle Handshake.

Two-cycle asynchronous signaling uses request (REQ) and acknowledge (ACK) signals:
Initially ACK and REQ are unasserted
Receiver requests data (signals readiness to accept data) by asserting REQ Sender detects change on REQ, puts data on DATA lines, then asserts ACK. Receiver detects change on ACK and reads data, then removes REQ. Sender detects change on REQ, removes data and removes ACK when
it is ready to send new data.

NOTE: The speed of communication is still limited. The faster system
must wait (idle clock cycles) at each data word.


FIFO


FIFO.

Exchange of data between two clock domains can be accomplished
using a FIFO (First In First Out) memory. Ports on one side of the FIFO
(writing data to memory) operate synchronously with clock A. Ports on
the other side (reading data from memory) operate synchronously with
clock B. FIFO acts as a buffer, enabling both systems to operate at their
full speed. The synchronous system A should monitor the "full" flag, so
that the FIFO does not overflow. The synchronous system B should
normally monitor the "empty" flag and read-data from the FIFO as soon
as it is available.
Both systems can operate at their full speed. (This may be limited by
the depth of FIFO).


Other methods include:

• Sending DATA only (i.e. using known data rate or recovering the
clock from data stream on the receiver side, etc.).

• Synchronising clocks (e.g. faster system works at a multiple clock
frequency of the slower system). This can be accomplished using
DLLs to recover the clock.
The speed of communication is limited. The faster system must wait
(idle clock cycles) at each data word.


I do not claim any originality in this article.

Sources;

www.eee.manchester.ac.uk/intranet/ug/coursematerial/2nd%20Year/EEEN20023-Digital%20Systems%20Design2/l9.pdf