Written by Tom on Wednesday 30/05/07
There are a couple of data-path conditions in VHDL design that will cause the code to fail, race condition and the opposite propagation delay.
Race Condition occurs when two flip-flops are directly coupled, running on the same clock. The output of A can violate the hold time on B input. This situation can be worsened if there is clock skew between each of the flip-flops.
The solution is to add a delay element between the two flip-flops to ensure that hold time violations do not occur.
Propagation Delay is corrected by using a technique called pipelining. A large complex logic component can cause a long propagation delay. This delay can become the limiting factor in the maximum operating frequency. If the combinatorial logic chain can be split into shorter stages, and registers inserted in-between the logic levels, then the maximum propagation delay (critical path) is shortened. This is known as "pipelining". The operations are now carried out over multiple clock cycles, increasing the latency (overall time of processing of a piece of data from input to output), however, the clock frequency can be increased thus increasing the throughput (note that a new input data
can be processed on each clock cycle). The overall system performance is therefore improved.
Critical Data Path.
The critical path in the above diagram, is from signals a and b through the adder to the multiplier.
The output of the adder is delayed by 10ns therefore signal c will reach the multiplier early w.r.t. a and b.
To fix the critical data path in the above, above example, pipeline registers are inserted as above. This ensures that output of the adder and qc arrive at the same time at the multiplier.
I do not claim any originality in this article.