Xemacs and VHDL tutorial.

Written by Tom on Friday 02/02/07

Xemacs is a highly configurable editor. It has a VHDL extension which is very powerful. In this article I will briefly outline the basics of Xemacs;


Adding the vhdl package.

Some nice features of the VHDL extension.


To install Xemacs(windows) download the installer from here. Just go OK/Yes to the default installation. When the installer is finished create a shortcut to the desktop.

Adding the vhdl package.

(1) On the menubar, choose Tools -> Packages -> Set Download Site ->Official Releases, then browse for a site near you.

(3) On the menubar, choose Tools -> Packages -> List and Install.

(4) Find the line corresponding to the vhdl package and press Return to mark it.

(5) Press the x key to download and install the package.

To create a new file in Xemacs select File->Open type in the name of required file ie ‘MyVHDL.vhdl’ click on the open button

Some nice features of the VHDL extension.

Rapid Code generation.

(1) Select VHDL->Template->Insert Header.

(2) Select VHDL->Template->Package->std_logic_1164.

A tip here the industry standard is std_logic_1164 if you choose to use numeric_std this is manufacture dependant.

(3) Select VHDL->Template->VHDL Construct 1->Entity.

You are prompted for a name, give it one. Next you are asked for generic interface signals fill it in or press enter to continue. Next prompt is for port interface signals, fill in as need be.

(4) Select VHDL->Template->VHDL Construct 1->Architecture.

Give it a name of ‘a’.

(5) Select VHDL->Template->Model->Example Model.

You have just inserted a template for a process complete with reset, all signals with <> need to be replaces with your signals. There we have it in one minute you have created a complete skeleton for you entity.

In the open file push the ‘>’ button twice you will notice the auto-complete to ‘=>’ this very handy also ‘<’ twice gives you ‘<=’.

Use the Tab key to auto complete a word key pressing until the correct word appears.

Set the line and column numbers visible via Options->Display->LineNumbers and Column Numbers. Make sure you save your setting via Options->Save Options to Custom File.

Test bench generation; Open a file with an entity, click anywhere within the entity and select VHDL->Port->Copy the command line will tell you when the action is complete. Next select VHDL->Port->Past as Test Bench give it a architecture name of lets say ‘a’ press enter and there you have a test bench ready to go. You just saved yourself an hours worth of coding by using Xemacs.

Syntax highlighting.
To enable syntax highlighting Select Options->Syntax Highlighting->In the buffer.