Simple fixed point divider VHDL code example.

Written by Tom on Monday 04/06/07


Here is a fixed point divider with remainder written in combinational logic.


a is the dividend.


b is the divisor.


y is the quotient.


rest is the remainder.


From GTKWaveSignals.JPG the results of the simulation can be seen.


Download the project from here.


Use the go.bat to compile and run GTKWave.