VHDL simple serial receiver code example.

Written by Tom on Wednesday 14/02/07

One of the easiest ways to communicate with an FPGA is via a standard RS232 serial port.
The IO pins from the FPGA are not likely to be RS232 compatible so you must use a voltage shifter like MAX232.

This example code is kicked off by the start bit and receives 8 bits of data after which the byte is made available via byteOut.

You can download the example code, test bench and signals from GTKWave from here.

Compilation instructions for GHDL and viewing with GKTWave.

ghdl -a simpleSerialRx.vhdl

ghdl -a simpleSerialRx_tb.vhdl

ghdl -e simpleSerialRx_tb

ghdl -r simpleSerialRx_tb --vcd= simpleSerialRx.vcd --stop-time=1us

gtkwave simpleSerialRx.vcd signals