Simple RAM block, VHDL example code

Written by Tom on Thursday 22/02/07


FPGA’s are useful in various number crunching applications. Being able to complete 32/64 bit multiplications every clock cycle you can process a lot of data quickly. The place to store the pre-processed and processed data is the RAM block.


You can get a simple VHDL RAM block from here.


From the GTKWaveSignals.jpg you can see that when the write enabled is active the data_out is set to ‘Z’ so can not be read. What ever the address is set to, is what is on data_out so if you are not writing you can read.


Compilation instructions for GHDL and viewing with GKTWave.


ghdl -a simpleRam.vhdl

ghdl -a simpleRam_tb.vhdl

ghdl -e simpleRam_tb

ghdl -r simpleRam_tb --vcd= simpleRam.vcd --stop-time=1us

gtkwave simpleRam.vcd signals