Simple RAM block with Bidirectional data bus, VHDL example code.

Written by Tom on Thursday 15/03/07


This is just a variation to the previously posted Simple RAM block example.


You can get a simple VHDL RAM block with Bidirectional data bus from here.


Note: When changing from IN to OUT you must drive the bidir data bus to high Z and vice versa.


Compilation instructions for GHDL and viewing with GKTWave.


ghdl -a simpleBiDiRam.vhdl

ghdl -a simpleBiDiRam_tb.vhdl

ghdl -e simpleBiDiRam_tb

ghdl -r simpleBiDiRam_tb --vcd= simpleBiDiRam.vcd --stop-time=1us

gtkwave simpleBiDiRam.vcd signals